Why Toves? I’ve developed Logisim for over twelve years, but over time I’ve found some inherent limitations that are deeply embedded in the system but prevent it from maturing to “the next level.” Rather than try to find some route to overcoming these several limitations within the current framework, I wanted to build on a replacement system from scratch. Hence this project.
Logisim represents a lot of accumulated work, so naturally replacing it will take a lot of work. Though I’ve put significant work into what Toves is today, it’s not very far. Right now, all Toves can do is allow you to build and simulate a simple circuit out of 2-input AND, OR, and NOT gates. No subcircuits, no multibit wires, not even copy-and-paste or opening a file. For now, what makes Toves interesting is primarily what’s under the hood, which I’ll discuss in later posts.
But while it’s hardly useful, I’ve now uploaded the first working version – version 0.0.1. While it’s not particularly useful, it’s there for you to look at and critique.
In this blog, I hope to chronicle the progress of Toves development. Some posts will present user-facing design decisions, seeking feedback on ways to improve. Others will describe internal architectural decisions, reflecting lessons learned the hard way from Logisim. My hope is that others will contribute comments, leading to ideas that ultimately will lead Toves to be even better than it would be if I worked in isolation.
To give you a taste of what to hope for from this project, here are a few of the features that I eventually hope to include in Toves, but which aren’t in Logisim:
- Diagonal wires [This is in Toves today: Horizontal/vertical is the default, but alt-drag creates a diagonal wire.]
- Canvas extends infinitely in all directions (rather than having a fixed upper left corner) [This is in Toves today.]
- Z-ordering of components preserved
- Drawing arbitrary shapes like rectangles or lines in a layout
- Modules of varying types – usually a layout (the only Logisim option), but a module might also be a memory, a truth table, or a state machine – and hopefully one day source code (perhaps written in Verilog)
- No delay in sending signals into a subcircuit (Logisim introduced a one-step delay when sending a signal into or out of a subcircuit)
- Bidirectional connections into subcircuits
- Eight-valued logic, allowing weakly-driven 1’s and 0’s – particularly useful for open-collector circuits
- An oscilloscope for viewing how signals change over time
- Components that must be “closed” once the simulation becomes inactive – particularly file and network I/O
- Components that “time out” after a period, like a monoflop.
- Tablet support under iOS and Android.
I invite you to follow along in the coming months – maybe years – and to participate in the discussion!
What features would you particularly like to see (or not see)?