Under the hood: Simulation data

Many of the biggest changes from Logisim to Toves are “under the hood,” some of the more important of which I’ll explain in the next few days. These changes are basically invisible to a user, though it has major implications for the code design and features provided.

This post will discuss the biggest of the changes: How circuits are represented during simulation. Logisim has just one representation of the circuit layout: During simulation, it remembers, “there’s a 0 at this coordinate, X at that coordinate” and so on. By contrast, as you build a layout, Toves “compiles” the physical layout into a separate data structure corresponding to the circuit’s logical connections. Toves represents a set of linked wire segments as a system of “nodes” and “links” between them. The simulation code has no knowledge of coordinates. It also forgets about components and subcircuits, dealing simply with a collection of “instances.”

Naturally, Logisim’s approach has some advantages. It is conceptually simpler, and it has less redundancy, so there are fewer data structures to keep “in sync.” By contrast, Toves maintains two redundant representations of the circuit – one representation used for drawing and editing, with another representation being used for simulation. Keeping these two representations in sync is tricky. In fact, I started work on this concept several times over the last several years before finally getting this version to work.

While Toves’s technique is more complex, there are of course important reasons to keep them separate. First is the efficiency angle. Actually, the Logisim approach has the potential to be more efficient for *drawing the circuit*, which works with the layout information but Toves must repeatedly map to the simulation to determine what values to draw. But for *simulating a circuit*, the Toves approach can potentially be faster – both because the data structure it’s working with is designed explicitly for simulation, and because the structure itself is simpler, providing more room for further optimization. So do we go for efficiency at drawing or at simulation? Well, there’s little reason to repaint the circuit more than 30 times a second, but we hope to execute thousands of simulation steps each second, so priority should go to simulation.

Another advantage to Toves’s approach is an issue of software architecture. Once you get past the complexity of maintaining a mapping between layout and simulation representations, Toves has the advantage of being cleanly broken into “layers”: At the bottom, you have the simulation model, then the simulation state on top of that, then the layout model, then the abstract GUI code (written to be independent of platform), then the actual GUI implementation. Toves tries to keep the layers more separate, with one-way dependencies between them; by contrast, Logisim is not very cohesive, with packages/namespaces freely depending on one another.

Finally, separating the simulation representation from the physical layout should make it easier to support project modules being defined not by a physical layout but by HDL code (whether Verilog or VHDL). With Logisim, we’d have to make up a fictional graphical layout corresponding to the textual code, whereas with Toves we can compile both the HDL code and the physical layout into the same underlying representation. Admittedly, support for HDL code is a long way off, but I’m hopeful that Toves will be ready for this when the time comes.